porting uboot on a new board(6) memory map

SDRAM, 256MB: 0x2000_0000 ~ 0x3000_0000
NAND flash, 256MB
   SMC_Bank 2: 0x900_0000 ~ 0x9800_0000 (128MB)
   SMC_Bank 3: 0x980_0000 ~ 0xA000_0000 (128MB)



S5PC100_Datasheet

porting uboot on a new board(5) board dependent code

- MACH-TYPE
   board/samsung/mango100/mango100.c
   int board_init(void)
   {
gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

porting uboot on a new board(4) start-up code

- arch/arm/cpu/u-boot.lds
   ENTRY(_start)
   SECTIONS
   {
. = 0x00000000;

- arch/arm/lib/vectors.S
   _start:
b reset

- arch/arm/cpu/armv7/start.S
   reset:
bl save_boot_params
   #ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_cp15
bl cpu_init_crit
   #endif
bl _main

   ENTRY(cpu_init_crit)
b lowlevel_init @ go setup pll,mux,memory
   ENDPROC(cpu_init_crit)

- board/samsung/mango100/lowlevel_init.S
   lowlevel_init:
/* setting SRAM */
ldr r0, =S5PC100_SROMC_BASE
/* for UART */
bl uart_asm_init
/* for TZPC */
bl tzpc_asm_init

porting uboot on a new board(3) creat a new board files and defconfig

VERSION = 2014
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc2


- config header
copy include/configs/smdkc100.h to include/configs/mango100.h

- board directory
copy board/samsung/smdkc100 to board/samsung/mango100

- defconfig
copy configs/smdkc100_defconfig configs/mango100_defconfig


- arch/arm/Kconfig
add these lines
   config TARGET_MANGO100
       bool "Support mango100"
   source "board/samsung/mango100/Kconfig"

-board/samsung/mango100/Kconfig

-board/samsung/mango100/Makefile

- update MAKEALL
need to modify???

- update Makefile
need to modify???

- arch/arm/config.mk

- arch/arm/cpu/armv7/config.mk

- include/autoconfig.mk
- include/autoconfig.mk.dep
   generated by Makefile

- include/config.h

Install 64 bits usb driver for S5PC100 SEC SMDK board

S5PC100 SEC SMDK board comes out as unknown device of "SEC S3C2410X Test B/D" on Win7 64 bits.

To install the driver attached, disable digital signature check first since the driver does not contain the digital signature.


bcdedit.exe -set loadoptions DDISABLE_INTEGRITY_CHECKS

bcdedit.exe -set TESTSIGNING ON

Restart the computer

Hmm... how do I insert a zip file in this post???

smdkc100_usb_driver_x64_only

porting uboot on a new board(2) troubleshoot "fixdep: Permission denied"

Error
HOSTCC  scripts/basic/fixdep
/bin/sh: scripts/basic/fixdep: Permission denied

Solution
mount options problem, so remount with default options.
$> mount /dev/sda2 /media/root/host

ARM cross compiler

I count on Linaro for ARM compiler.

http://www.linaro.org/downloads/


Working group for toolchain
https://wiki.linaro.org/WorkingGroups/ToolChain

Toolchain FAQ
https://wiki.linaro.org/WorkingGroups/ToolChain/FAQ

porting uboot on a new board(1) homepage, git uri, configuration, and build

Homepage
http://www.denx.de/wiki/U-Boot/WebHome

Git URL
git://git.denx.de/u-boot.git
http://git.denx.de/u-boot.git

Configuration
http://www.denx.de/wiki/view/DULG/UBootConfiguration

Build
make distclean
make smdkc100_defconfig
make all

tftp server on ubuntu

Install required packages
apt-get install xinetd tftpd tftp

Create /etc/xinetd.d/tftp and put this contents
service tftp
{
protocol        = udp
port            = 69
socket_type     = dgram
wait            = yes
user            = nobody
server          = /usr/sbin/in.tftpd
server_args     = /tftpboot
disable         = no
wait = yes
}

Create a folder /tftpboot for tftp base directory

Restart the xinetd service.
$ sudo /etc/init.d/xinetd stop
$ sudo /etc/init.d/xinetd start

Original source from
http://mohammadthalif.wordpress.com/2010/03/05/installing-and-testing-tftpd-in-ubuntudebian/

root log-in on Ubuntu

Ubuntu 12.04
sudo passwd root
sudo sh -c 'echo "greeter-show-manual-login=true" >> /etc/lightdm/lightdm.conf'

Ubuntu 14.04
sudo passwd root
sudo sh -c 'echo "greeter-show-manual-login=true" >> /usr/share/lightdm/lightdm.conf.d/50-ubuntu.conf'

Setting C variable from ASM

- in c code
unsigned int g_asm_var = 0xdead; //initialization seems mandatory??
EXPORT_SYMBOL(g_asm_var);

- in assem code
.global g_asm_var;



    stmdb sp!, {r11} //optional
    ldr    r11, =g_asm_var
    str    \ttbr1, [r11] // str r3, [r11]
    ldmia    sp!, {r11} //optional

     stmdb sp!, {r0 - r3}
    ldr    r0, =g_ttbr_smp
    ldr    r1, =g_ttbr_up
    mov    r2, #TTB_FLAGS_SMP
    mov    r3, #TTB_FLAGS_UP
    str    r2, [r0]
    str    r3, [r1]
    ldmia    sp!, {r0 - r3}

ARM ASM branch

  b . //branch to self
  b 2f //branch to label 2 forward
1:
  b 1b //branch to label 1 backward
  b 1f //branch to label 1 forward
1:
  ..........
2:

setting TTBR1 - 3.6.x

proc-v7-2level.S

    .macro    v7_ttb_setup, zero, ttbr0, ttbr1, tmp
    mcr    p15, 0, \zero, c2, c0, 2    @ TTB control register
    ALT_SMP(orr    \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
    ALT_UP(orr    \ttbr0, \ttbr0, #TTB_FLAGS_UP)
    ALT_SMP(orr    \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
    ALT_UP(orr    \ttbr1, \ttbr1, #TTB_FLAGS_UP)
    mcr    p15, 0, \ttbr1, c2, c0, 1    @ load TTB1
    .endm

setting TTBR1 - 3.2.x

proc-v7.S

__v7_setup:
 adr r12, __v7_setup_stack  @ the local stack
 stmia r12, {r0-r5, r7, r9, r11, lr}
 bl v7_flush_dcache_all
 ldmia r12, {r0-r5, r7, r9, r11, lr}

 mrc p15, 0, r0, c0, c0, 0  @ read main ID register
 and r10, r0, #0xff000000  @ ARM?
 teq r10, #0x41000000
 bne 3f
 and r5, r0, #0x00f00000  @ variant
 and r6, r0, #0x0000000f  @ revision
 orr r6, r6, r5, lsr #20-4  @ combine variant and revision
 ubfx r0, r0, #4, #12   @ primary part number

 /* Cortex-A8 Errata */
 ldr r10, =0x00000c08  @ Cortex-A8 primary part number
 teq r0, r10
 bne 2f
#ifdef CONFIG_ARM_ERRATA_430973
 teq r5, #0x00100000   @ only present in r1p*
 mrceq p15, 0, r10, c1, c0, 1  @ read aux control register
 orreq r10, r10, #(1 << 6)  @ set IBE to 1
 mcreq p15, 0, r10, c1, c0, 1  @ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
 teq r6, #0x20   @ only present in r2p0
 mrceq p15, 0, r10, c1, c0, 1  @ read aux control register
 orreq r10, r10, #(1 << 5)  @ set L1NEON to 1
 orreq r10, r10, #(1 << 9)  @ set PLDNOP to 1
 mcreq p15, 0, r10, c1, c0, 1  @ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
 teq r6, #0x20   @ only present in r2p0
 mrceq p15, 1, r10, c9, c0, 2  @ read L2 cache aux ctrl register
 tsteq r10, #1 << 22
 orreq r10, r10, #(1 << 22)  @ set the Write Allocate disable bit
 mcreq p15, 1, r10, c9, c0, 2  @ write the L2 cache aux ctrl register
#endif
 b 3f

 /* Cortex-A9 Errata */
2: ldr r10, =0x00000c09  @ Cortex-A9 primary part number
 teq r0, r10
 bne 3f
#ifdef CONFIG_ARM_ERRATA_742230
 cmp r6, #0x22   @ only present up to r2p2
 mrcle p15, 0, r10, c15, c0, 1  @ read diagnostic register
 orrle r10, r10, #1 << 4  @ set bit #4
 mcrle p15, 0, r10, c15, c0, 1  @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
 teq r6, #0x20   @ present in r2p0
 teqne r6, #0x21   @ present in r2p1
 teqne r6, #0x22   @ present in r2p2
 mrceq p15, 0, r10, c15, c0, 1  @ read diagnostic register
 orreq r10, r10, #1 << 12  @ set bit #12
 orreq r10, r10, #1 << 22  @ set bit #22
 mcreq p15, 0, r10, c15, c0, 1  @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
 teq r5, #0x00200000   @ only present in r2p*
 mrceq p15, 0, r10, c15, c0, 1  @ read diagnostic register
 orreq r10, r10, #1 << 6  @ set bit #6
 mcreq p15, 0, r10, c15, c0, 1  @ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 ALT_SMP(cmp r6, #0x30)   @ present prior to r3p0
 ALT_UP_B(1f)
 mrclt p15, 0, r10, c15, c0, 1  @ read diagnostic register
 orrlt r10, r10, #1 << 11  @ set bit #11
 mcrlt p15, 0, r10, c15, c0, 1  @ write diagnostic register
1:
#endif

3: mov r10, #0
 mcr p15, 0, r10, c7, c5, 0  @ I+BTB cache invalidate
#ifdef CONFIG_MMU
 mcr p15, 0, r10, c8, c7, 0  @ invalidate I + D TLBs
 mcr p15, 0, r10, c2, c0, 2  @ TTB control register
 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
 mcr p15, 0, r8, c2, c0, 1  @ load TTB1
 ldr r5, =PRRR   @ PRRR
 ldr r6, =NMRR   @ NMRR
 mcr p15, 0, r5, c10, c2, 0  @ write PRRR
 mcr p15, 0, r6, c10, c2, 1  @ write NMRR
#endif
 dsb     @ Complete invalidations
#ifndef CONFIG_ARM_THUMBEE
 mrc p15, 0, r0, c0, c1, 0  @ read ID_PFR0 for ThumbEE
 and r0, r0, #(0xf << 12)  @ ThumbEE enabled field
 teq r0, #(1 << 12)   @ check if ThumbEE is present
 bne 1f
 mov r5, #0
 mcr p14, 6, r5, c1, c0, 0  @ Initialize TEEHBR to 0
 mrc p14, 6, r0, c0, c0, 0  @ load TEECR
 orr r0, r0, #1   @ set the 1st bit in order to
 mcr p14, 6, r0, c0, c0, 0  @ stop userspace TEEHBR access
1:
#endif
 adr r5, v7_crval
 ldmia r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
 orr r6, r6, #1 << 25  @ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
 orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
 bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
    mrc p15, 0, r0, c1, c0, 0  @ read control register
 bic r0, r0, r5   @ clear bits them
 orr r0, r0, r6   @ set them
 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
 mov pc, lr    @ return to head.S:__ret
ENDPROC(__v7_setup)

TTBR0 and switch_mm

switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)

    cpu_switch_mm(next->pgd, next);

#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)

#define cpu_do_switch_mm processor.switch_mm

proc-v7-2level.S
//cpu_v7_switch_mm(pgd_phys, tsk)
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
mov r2, #0
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
#ifdef CONFIG_ARM_ERRATA_430973
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif
#ifdef CONFIG_ARM_ERRATA_754322
dsb
#endif
mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
isb
1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
isb
#ifdef CONFIG_ARM_ERRATA_754322
dsb
#endif
mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb
#endif
mov pc, lr
ENDPROC(cpu_v7_switch_mm)